Background I was contacted to discuss a restoration of an Apollo Guidance Computer, the block II type that was used on all the manned Apollo missions. Until I have clearance to say more, I can't discuss the location, ownership or other identifying details, but I can post about the AGC itself and the detailed studying I have been doing to prepare for this task.
AGC constructionThe block II AGC is a general purpose computer constructed entirely of logic gates (and power supplies and memory of course), no microprocessors. The logic was entirely built with a single IC type, a dual NOR gate, each one triple input. These ICs are RTL, resistor-transistor logic, which preceded both diode-transistor logic (DTL) and then transistor-transistor logic (TTL). RTL gates are very simple. Each input is coupled through a resistor to the base of a transistor. The emitter is tied to ground and the collector has the output lead and a pullup resistor to the positive voltage source. In the AGC case, this is +4V. When a positive voltage is presented on the input, the transistor conducts and pulls the output down to almost ground level. When no input voltage, the transistor is off and the output is pulled up to nearly +4V. The triple input NOR gate has three transistors, with three base resistors, and the collectors all tied together, making use of a single pullup resistor for the output. If any or all of the three inputs has a positive voltage, one or more of the transistors are conducting and pull the output down towards ground, otherwise with all inputs at 0, the output floats up to +4. These dual-NOR gate chips have two of the above circuits, thus it has six transistors and eight resistors on the chip. It was built in a flat pack, a rectangular flat shape with ten leads arranged five per long side. The chips are mounted on a multi layer printed circuit board, but welded to the pad rather than soldered. Soldering was not considered reliable enough to use with a machine that has to resist up to 50g of vibration/acceleration. The multilayer PCB was quite advanced for the time. It was seven layers. This was designed and manufactured in the first half of the 1960s. The top layer had the pads for the flat pack ICs to be welded, and tabs along the bottom of that layer or interconnects to the board. Next was the voltage layer. In the middle were three layers used for circuit interconnects. A ground layer sat below them and a final interconnect layer was on the bottom of the sandwich. A printed circuit board was 9 inches wide and just over 1 inch tall, with mounting spots for 60 ICs. Thus, one PCB held 120 NOR gates of logic. The I/O interconnect tabs along the bottom edge of the PCB were in two groups of 40 and a middle group of 58, thus the PCB featured up to 138 connections to the backplane connector. Wires were connected between these tabs and the Malco mini-WASP connectors on the base of the logic module. The logic module was sealed in epoxy potting, although some testing and development machines were left unpotted for each debugging access. Aluminum modules held two of these PCBs, one per side, with 276 pins of I/O on the bottom. This module plugged into an aluminum tray with a backplane across the bottom.
The backplane had connectors for all the logic modules, up to 240 connections each, with wire-wrap connecting all those pins together. The AGC had two such trays - the logic tray and the memory tray - which were magnesium, bolted together and put on a cold plate, forming a 24 inch by 12.5 inch structure that was 6.5 inches deep. Liquid cooling was supplied to the cold plate to remove the heat during operation. The AGC was supplied with 28V DC and had internal power supplies to produce the lower voltages, such as 4V and 14V, needed for logic and memory. The main oscillator ran at 2.048 MHz and was used as a common timing source to drive all the attached electronics in the spacecraft. Memory used ferrite cores. The regular read-write memory (called erasable) was 2048 locations of 16 bit words. The remainder of the memory was read-only (called fixed), built as core rope assemblies. The erasable memory needed space for 32,768 cores to hold the 2K of data, but the design of rope memory provided 36K words with only 3,072 cores. Each core, which was larger than the lithium ferrite core used with erasable memory, is a different material and had many wires threaded through it A core could hold 192 bits of information because the actual information storage was the wiring of sense lines. The remainder of the wiring was used to select which 16 of the 3072 cores to flip on and off. If a sense wire ran through that core, it produced a 1 on output while the wires that bypassed cores had a 0 output. The reality was a bit more complex, because the memory was arranged in six core rope modules of 512 cores each (6K words). Inside the module were four planes of 128 cores each. In reality more than 16 cores would be flipped but selection logic and diodes assured that we picked off only the 16 bits that were desired. No individual core would ever have more than 128 sense lines through it (1 bits assigned).
During testing and software development, various core rope simulators were plugged into the AGC in lieu of the actual fixed memory modules. Some would override the core rope module, others replaced the six modules with plugs connected to the simulator. This allowed testing of software changes before the design was frozen and the Raytheon factor wove the sense lines to form a final rope module.