Thank you for responding.
I mean to ask this question on a TECHNOLOGICALLY ADVANCED level. Presently I find NO INFORMATION WHATSOEVER available in publicly on this topic, and it really surprises me.
I would like to learn from you/Intel, the MAXIMUM PCIe data bandwidth that one single JHL6540/DSL6540 controller has.
I understand that laptop manufacturers implement your JHL6540/DSL6540 in DIFFERENT ways, which have performance impact.
Specifically, laptop designs that would run your JHL6540/DSL6540 BELOW its full capacity that I am aware of, are
- How many PCIe lanes that the JHL6540/DSL6540 is given - it's a x4 PCIe v3 lanes chip (giving 32gbps full-duplex bandwidth upstream), however can be operated also if given only x2 PCIe v3 lanes (giving 16gbps full-duplex bandwidth upstream),
- For U series Intel CPU:s, the laptop's OPI configuration, specifically if it's set to 4GT/s (meaning optimized for performance) or 2GT/s (meaning optimized for battery) - I understand this is a CPU setting that's specified by a laptop manufacturer's BIOS and therefore manufacturer-specific, ref. https://egpu.io/ultrabook-buyers-guide-external-gpu/#opi , https://www.reddit.com/r/eGPU/comments/7vb0gg/u_series_chips_pcie_lanes_and_thunderbolt_3/ .
- (For ULV processors where the x4 PCIe lanes go from the PCH, rather than are routed directly to the CPU as is the case in quad-core laptop processors, I would understand if the CPU's IO load to other PCH-connected devices such as the laptop's internal SSD or WIFI, could have a performance impact on Thunderbolt 3 throughput.)
For this question however, I will presume that the laptop manufacturer has dedicated x4 PCIe v3 lanes to your JHL6540/DSL6540, and that the laptop is operating in 4GT/s mode.
(If in the list above I missed any major factors impacting the possible JHL6540/DSL6540 real-world throughput, feel free to fill in the blanks. Anyhow I guess for this question, this list suffices.)
And last now, going back to https://thunderbolttechnology.net/sites/default/files/Thunderbolt3_TechBrief_FINAL.pdf , I understand from this document that the JHL6540/DSL6540's total bandwidth for ONE Thunderbolt 3 port must be 22gbps full-duplex.
Now, please explain to me, what is the JHL6540/DSL6540's total maximum PCIe data bandwidth, for BOTH Thunderbolt 3 ports?
I have two working hypotheses for what it could be:
- The JHL6540/DSL6540 has an internal 22gbps full-duplex cap, which means you have a "pool" of 22gbps shared full-duplex bandwidth between both TB3 ports, e.g. if you do 15gbps PCIe data on one port, then the other port will have 7gbps.
- The JHL6540/DSL6540 has internal 32gbps full-duplex, as in its upper limit is defined by its upstream PCIe bandwidth, and both TB3 ports share these 32gbps in a pooled fashion with each TB3 port being able to eat at most 22gbps at a given time, meaning if you do 22gbps PCIe data on one TB3 port (that is, you saturate the whole link), then you will STILL be able to do another 10gbps PCIe data separately on the other TB3 port.
The above is extremely valuable to know when buying Thunderbolt 3 gear:
For instance, an eGPU should normally be given an own, dedicated Thunderbolt 3 port. If the JHL6540/DSL6540 has 32gbps total PCIe data bandwidth, then this means you have 10gbps potential extra bandwidth on the second Thunderbolt 3 port available, which means that you could run, for instance, a 10gbps Ethernet adapter, or an external PCIe NVMe SSD drive, and as long as that second TB3 port has less than 10gbps data in each direction it will *NOT* interfere with the eGPU:s operation, and, on the rare occasions that the data on the second TB3 port would be in the 10-22gbps interval, then this would cause no latency or slowdown in eGPU operation also, presuming that the eGPU is operating at <= 10gbps at that time.
If on the other hand both TB3 ports share a total 22gbps bandwidth pool, then from a total bandwidth point of view which TB3 port eGPU, 10gbps ethernet and PCIe NVMe SSD are connected to, does not matter, and considerations would instead be made relating to any / the latency and bandwidth overhead incurred by daisy chaining, e.g. total number of devices connected in daisy chain on the TB3 port, latency and bandwidth impact from how many steps downstream a device is located in the daisy chain.
I hope my examples and elaborations above clarified the intention and scope of the question. It's extremely important that there is a public figure explaining this.
I could deduce this information by benchmarking also, however that requires ~1000-2000 worth of equipment and would take me a full day. Your company (Intel) has designed this technology, you know your design specs already, there is no reason for you to not share it publicly.
Looking forward to your response ASAP, thanks!